SIR_LP_MODE=Val_0x0, SIR_MODE=Val_0x0
Module Configuration Register
| APB_DATA_WIDTH | The value of this field defines the APB data width. 2 (Val_0x2): APB data width is 32 bits |
| AFCE_MODE | The value of this bit defines the AFCE mode. 1 (Val_0x1): AFCE mode enabled |
| THRE_MODE | The value of this bit defines the THRE mode. 1 (Val_0x1): THRE mode enabled |
| SIR_MODE | The value of this bit defines the SIR mode. 0 (Val_0x0): SIR mode disabled |
| SIR_LP_MODE | The value of this bit defines the SIR low power mode. 0 (Val_0x0): SIR_LP mode disabled |
| ADDITIONAL_FEAT | The value of this bit defines the additional features. 1 (Val_0x1): Additional features enabled |
| FIFO_ACCESS | The value of this bit defines the FIFO access. 1 (Val_0x1): FIFO ACCESS enabled |
| FIFO_STAT | The value of this bit defines the FIFO status. 1 (Val_0x1): FIFO_STAT enabled |
| SHADOW | The value of this bit defines the shadow registers. 1 (Val_0x1): SHADOW enabled |
| UART_ADD_ENCODED_PARAMS | The value of this bit defines the capability of reading encoded information about module configuration settings. Reading 1 in this bit means that the capability of reading this encoded information via software has been enabled. 1 (Val_0x1): UART_ADD_ENCODED_PARAMS enabled |
| DMA_EXTRA | The value of this bit defines the DMA. 1 (Val_0x1): DMA_EXTRA enabled |
| FIFO_MODE | The value of this field defines the FIFO mode. 2 (Val_0x2): FIFO mode is 32 |